A new kind of Nand chip package promises slimmer devices

Samsung Electronics has developed a new kind of chip package that stacks several chips together into a smaller space. The move will also enable devices such as memory cards and phone handsets that contain chips to be made slimmer.

The company said it plans to ship a 16Gbit Flash memory component using stacked 2Gbit Nand chips in early 2007. Later, Samsung will extend the technique to produce system-in-package solutions that stack a processor with one or more memory chips, and high-capacity DRAM packages for servers.

The wafer-level processed stack package (WSP) arranges a number of silicon dies on top of each other inside a chip package to save space. This technique is already used in multi-chip packages (MCPs), but Samsung has developed a way to route inter-chip connections through small vertical holes in the silicon, instead of at the edge of the chips. This enables the chips to be packed more closely together, according to Samsung, making its chips 30 percent thinner and with a 15 percent smaller footprint than an MCP.

As a side effect, the WSP method reduces the length of the electrical interconnections, which can boost chip performance, Samsung said. WSP will prove useful in new handset designs that require lower power consumption combined with higher performance and higher component density.