Intel has detailed its upcoming activities, including some info on Nehalem
Intel has laid out its future product roadmap, including a forthcoming six-core upgrade to its Xeon processor line, details of its next micro-architecture codenamed Nehalem, future 32nm chips, and technology with which it plans to meet requirements for high-performance graphics and visualisation.
Its first six-core x86 processor, code-named Dunnington, is due in the second half of 2008. Based on Intel's current Penryn technology, the chips will be socket-compatible with current quad-core parts, and add a 16MB L3 cache in addition to the extra cores.
Another key feature of Dunnington will be FlexMigration technology, which enables live virtual machine workloads to be moved between processors in a server farm regardless of the micro-architecture. Previously, all processors had to be identical in micro-architecture to support migration of a virtual machine while running.
Intel vice president Stephen Smith said that Dunnington will provide better energy efficiency as well as increased performance. "Expect a double-digit performance increase," he said.
Intel also expects to start production of its first Nehalem chips in the fourth quarter of 2008. This new micro-architecture is modular, enabling Intel to put together a chip from various building blocks and scale from 2 to 8 cores. This will allow the firm to target laptops right through to high-performance servers with the same basic architecture.
The first Nehalem chip will be a four-core part that also introduces an integrated on-chip memory controller and Intel's QuickPath Interconnect, a new point-to-point link for high-speed communication between processors and the rest of the system, similar to rival AMD's HyperTransport. It will be accompanied by a chipset called Tylersburg.
Nehalem has a number of enhancements that are expected to boost performance over existing Intel chips. Each core will be able to execute two code threads simultaneously, while the integrated memory controller will have three memory channels supporting DDR3 memory at up 1333MHz clock speeds.
A new L3 cache will be shared between all cores on each chip, operating an inclusive cache policy. This feature means that the L3 cache serves as a snoop filter for information held in the other cores, which will help with scalability in future, Intel said.
"As we add more cores in future, each core will avoid the pain of having to do cache snoops themselves," explained Ronak Singhal, principal engineer at Intel's Digital Enterprise Group.
The next generation of Intel's Itanium family, codenamed Tukwila, is due by the end of 2008 and will also feature the integrated memory controller and QuickPath Interconnect technology.
Intel said it aims to introduce its first 32nm chips in the 2009-2010 timeframe. The first of these will be a die-shrink of Nehalem, and codenamed Westmere. These will be followed by a new micro-architecture called Sandy Bridge, which will introduce new instructions for vector processing known as Advanced Vector Extensions (AVX), which will boost floating-point performance by doubling data width to 256bits.
Finally, Intel also gave more details on Larrabee, a forthcoming processor line aimed at very demanding graphics and visualisation applications. Each chip will have multiple cores, each one of which runs a modified x86 instruction set with added vector processing instructions and a coherent cache across the whole die.
Smith said that this architecture enabled programmers familiar with the PC architecture to put their skills to creating applications for medical imaging and 3D modelling, such as that seen in animated movies.
The chips could scale up to teraflop levels of performance, and are expected to be included in future graphics cards, according to Smith. Larrabee will be demonstrated later this year, Intel said, but no firm availability date has been given.
Intel has laid out its future product roadmap, including a forthcoming six-core upgrade to its Xeon processor line, details of its next micro-architecture codenamed Nehalem, future 32nm chips, and technology with which it plans to meet requirements for high-performance graphics and visualisation.
Its first six-core x86 processor, code-named Dunnington, is due in the second half of 2008. Based on Intel's current Penryn technology, the chips will be socket-compatible with current quad-core parts, and add a 16MB L3 cache in addition to the extra cores.
Another key feature of Dunnington will be FlexMigration technology, which enables live virtual machine workloads to be moved between processors in a server farm regardless of the micro-architecture. Previously, all processors had to be identical in micro-architecture to support migration of a virtual machine while running.
Intel vice president Stephen Smith said that Dunnington will provide better energy efficiency as well as increased performance. "Expect a double-digit performance increase," he said.
Intel also expects to start production of its first Nehalem chips in the fourth quarter of 2008. This new micro-architecture is modular, enabling Intel to put together a chip from various building blocks and scale from 2 to 8 cores. This will allow the firm to target laptops right through to high-performance servers with the same basic architecture.
The first Nehalem chip will be a four-core part that also introduces an integrated on-chip memory controller and Intel's QuickPath Interconnect, a new point-to-point link for high-speed communication between processors and the rest of the system, similar to rival AMD's HyperTransport. It will be accompanied by a chipset called Tylersburg.
Nehalem has a number of enhancements that are expected to boost performance over existing Intel chips. Each core will be able to execute two code threads simultaneously, while the integrated memory controller will have three memory channels supporting DDR3 memory at up 1333MHz clock speeds.
A new L3 cache will be shared between all cores on each chip, operating an inclusive cache policy. This feature means that the L3 cache serves as a snoop filter for information held in the other cores, which will help with scalability in future, Intel said.
"As we add more cores in future, each core will avoid the pain of having to do cache snoops themselves," explained Ronak Singhal, principal engineer at Intel's Digital Enterprise Group.
The next generation of Intel's Itanium family, codenamed Tukwila, is due by the end of 2008 and will also feature the integrated memory controller and QuickPath Interconnect technology.
Intel said it aims to introduce its first 32nm chips in the 2009-2010 timeframe. The first of these will be a die-shrink of Nehalem, and codenamed Westmere. These will be followed by a new micro-architecture called Sandy Bridge, which will introduce new instructions for vector processing known as Advanced Vector Extensions (AVX), which will boost floating-point performance by doubling data width to 256bits.
Finally, Intel also gave more details on Larrabee, a forthcoming processor line aimed at very demanding graphics and visualisation applications. Each chip will have multiple cores, each one of which runs a modified x86 instruction set with added vector processing instructions and a coherent cache across the whole die.
Smith said that this architecture enabled programmers familiar with the PC architecture to put their skills to creating applications for medical imaging and 3D modelling, such as that seen in animated movies.
The chips could scale up to teraflop levels of performance, and are expected to be included in future graphics cards, according to Smith. Larrabee will be demonstrated later this year, Intel said, but no firm availability date has been given.
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