Rambus unveils new features to give a memory architecture they say can deliver 1 Terabyte per second

Chip interface vendor Rambus has unveiled an initiative aimed at producing a memory architecture capable of moving data to processors at a rate of one terabyte per second.

Rambus senior engineering vice president Kevin Donnelly said that Rambus aims to, "Drive memory signaling technology to performance levels that are an order of magnitude greater than what can be achieved today."

As chip vendors like Intel and AMD pack more processors into multi-core systems, the bottleneck would move to how fast the data could be delivered to these systems from memory.

Rambus said that the new architecture has unique features which combine to give 1TB/s. Firstly a data rate delivering 32 bits of data per clock cycle on each I/O – current double data rate (DDR) systems transfer two bits of data per clock cycle on each I/O. Next is what Rambus say is the industry's first Fully Differential Memory Architecture (FDMA) with differential signaling for data and command/address (C/A) and finally, FlexLink, the industry's first full-speed, point-to-point C/A link.

So a future system-on-a-chip connected to 16 DRAM devices, each operating at 16Gbit/s with a 4-byte (32 bit) wide interface, would give 1 terabyte per second of memory bandwidth.