Firm reduces the size of a stacked set of semiconductors

Samsung Electronics today announced that it has developed a small-footprint memory technology through a technique which reduces the size of a stacked set of semiconductors.

Samsung’s wafer-level processed stack package (WSP) of high density memory chips was created using 'through silicon via' (TSV) interconnection technology. WSP actually reduces the physical size of a stacked set of semiconductor chips, while greatly improving overall performance.

Samsung said WSP is widely seen as the next generation in package technologies, and can be applied to all types of hybrid packages, including memory and processors, to deliver higher speed and higher density with minimum use of chip space.

Using this technology, mobile device and consumer electronics manufacturers will gain better electrical performance, well suited for slimmer, high-performance handset designs that provide longer battery time.

Samsung's first WSP is a 16Gb memory solution that stacks eight 2Gb NAND chips. The WSP generates a much smaller multi-chip package (MCP), which is the current mainstream solution for designing miniaturized, high-capacity memory devices. Samsung's eight-chip WSP prototype sample, which vertically stacks eight 50-micrometer, 2Gb NAND flash die, is 0.56 millimeters in height.

The chips in today's MCPs are connected by wire bonding, which requires vertical gaps between dies that are tens of microns wide and horizontal spaces on the package board that are hundreds of microns wide to accommodate the wire connections.

By contrast, WSP forms micron-sized holes that penetrate through the silicon vertically to connect circuits directly, eliminating the need for gaps of extra space and wires protruding beyond the sides of the die. Due to these adv antages, WSP has a 15-per cent smaller footprint and is 30 per cent thinner than an equivalent wire-bonded MCP solution.