Process is 50 per cent more efficient than 90nm
Samsung Electronics claims to be the first manufacturer to mass produce 512Mb DDR2 DRam on an 80 nanometre scale.
The Korean giant said that its 80nm process technology allows the firm to increase production efficiency by 50 per cent over the previous 90nm process.
"With demand for DDR2 at its highest level since its market debut in 2004, our 80nm technology allows us to more efficiently support the sustained demand growth expected in the DDR2 marketplace this year," said Tom Trill, director of DRam marketing at Samsung Semiconductor.
The company said that it was able to smoothly transition from 90nm to 80nm because it used many of the basic features of 90nm geometries, and required minimal upgrades to its fabrication lines.
The move to 80nm circuitry was accelerated by the use of a recess channel array transistor (RCAT). This 3D transistor layout greatly enhances the refresh rate, which is a critical element in data storage.
RCAT also reduces cell area coverage, which allows for increased process scaling by freeing up space for chip-per-wafer growth.
According to Gartner Dataquest, DDR2 memory will comprise over 50 per cent of the entire DRam market in 2006.
Samsung Electronics claims to be the first manufacturer to mass produce 512Mb DDR2 DRam on an 80 nanometre scale.
The Korean giant said that its 80nm process technology allows the firm to increase production efficiency by 50 per cent over the previous 90nm process.
"With demand for DDR2 at its highest level since its market debut in 2004, our 80nm technology allows us to more efficiently support the sustained demand growth expected in the DDR2 marketplace this year," said Tom Trill, director of DRam marketing at Samsung Semiconductor.
The company said that it was able to smoothly transition from 90nm to 80nm because it used many of the basic features of 90nm geometries, and required minimal upgrades to its fabrication lines.
The move to 80nm circuitry was accelerated by the use of a recess channel array transistor (RCAT). This 3D transistor layout greatly enhances the refresh rate, which is a critical element in data storage.
RCAT also reduces cell area coverage, which allows for increased process scaling by freeing up space for chip-per-wafer growth.
According to Gartner Dataquest, DDR2 memory will comprise over 50 per cent of the entire DRam market in 2006.
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